Today's modern digital electronic circuits operate by propagating digital signals (binary "1's" and "0's") between different combinational elements (i.e., logic gates) and/or sequential elements (i.e., flip-flops). The proper operation of most digital circuits requires that signals propagate along various signal paths within the circuit during a predetermined interval, usually the period between successive clock signals. The failure of a signal to propagate along one or more such signal paths during a clock period usually gives rise to an error known as a delay fault.
Presently, the technique most commonly relied upon to verify the operation of a digital circuit is the so-called "stuck-at fault" test. The stuck-at fault test presumes that the faults, if any, in a digital circuit under test are characterized by a fixed signal level (a "1" or a "0") at an input or output of one or more elements in the circuit irrespective of all other signals in the circuit. Stuck-at fault testing is typically accomplished by successively applying each of a set of selected test vectors to the input(s) of the digital circuit to cause the circuit to generate a known response under normal (defect-free) operating conditions. Should one or more stuck-at faults exist (i.e., the signal at a terminal of one or more elements is "stuck at" a particular level), then the response to one or more of the vectors will differ from the expected response. While the stuck-at testing technique is useful for revealing most types of faults, the technique may not reveal all possible delay faults that may exist.
The increasing speed of today's digital circuits has led to an increased interest in establishing a more reliable technique for detecting the presence of delay faults. In his paper "Model for Delay Faults Based Upon Paths", published in the Conference Proceedings of the International Test Conference (1985), at pages 342-349, G. L. Smith proposes detecting delay faults along a signal path by propagating one of six values from a first set of latches to the logic portion of a circuit under test. A second set of latches is provided to hold the signature generated by the logic portion following propagation of the selective value. By determining whether a designated value has been propagated from the input latch to the output latch within a predetermined interval, a delay fault can be determined.
The technique of Smith presupposes that the input latches are directly accessible from a primary circuit input and that the output latches are directly observable from a primary circuit output. Unfortunately, many digital circuits do not conform to such an architecture. While it is possible to modify a non-conforming circuit to add the necessary latches required to practice the Smith technique, such a modification will lead to an increase in the circuit overhead which is undesirable.
Thus, there is a need for a technique for detecting delay faults which is suitable for a wide variety of digital circuits.